/*-----------------------------------------------------------------------------
Student2013
Created (30.09.2012)
Created by Alina Ivanova
Version 1.0
main project
project for 2013 student
-------------------------------------------------------------------------------

-------------------------------------------------------------------------------
-- Verilog Student2013
-------------------------------------------------------------------------------*/
module Student2013
#(
// Parameter Declarations
	parameter SIZE_ADC_DATA                                  = 11;
	parameter SIZE_FILTER_DATA                               = 25;
	parameter SIZE_AFTER_FILTER_DATA                         = 15;
	parameter SIZE_DELAY                                     = 7;
	parameter DELAY_DATA                                     = 14;
	parameter l                                              = 6)
(
//-----------------------------------------------------------------------------
// Input Ports
//-----------------------------------------------------------------------------
	input  wire                                              reset,
	input  wire                                              clk,
//-----------------------------------------------------------------------------
	input  wire                                              test_overlay,
	input  wire                                              test_rate,
	input  wire [SIZE_DELAY:0]                               test_delay,
//-----------------------------------------------------------------------------
// Output Ports
//-----------------------------------------------------------------------------
	output wire [SIZE_ADC_DATA:0]                            output_data,
//-----------------------------------------------------------------------------
	output wire [SIZE_AFTER_FILTER_DATA:0]                   output_data_v1,
	output wire [SIZE_AFTER_FILTER_DATA:0]                   output_data_v2,
	output wire [SIZE_AFTER_FILTER_DATA:0]                   output_data_v3,
	output wire [SIZE_AFTER_FILTER_DATA:0]                   output_data_v4,
	output wire [SIZE_AFTER_FILTER_DATA:0]                   output_data_v5,
	output wire [SIZE_AFTER_FILTER_DATA:0]                   output_data_v6);
//-----------------------------------------------------------------------------
// Signal declarations
//-----------------------------------------------------------------------------
// ExpSigGen
	wire        [SIZE_ADC_DATA:0]                            output_data_exp_sig_gen;
//-----------------------------------------------------------------------------
// Signal Section
//-----------------------------------------------------------------------------
	assign output_data                                       = output_data_exp_sig_gen;
//-----------------------------------------------------------------------------
// Sub Module Section
//-----------------------------------------------------------------------------
	exp_sig_gen ExpSigGen (
		.clk                                                  (clk),
		.reset                                                (reset),
		.overlay                                              (test_overlay),
		.rate                                                 (test_rate),
		.delay                                                (test_delay),
		.output_data                                          (output_data_exp_sig_gen));

	v1_filter FilterV1 (
		.clk                                                  (clk),
		.reset                                                (reset),
		.input_data                                           (output_data_exp_sig_gen),
		.output_data                                          (output_data_v1));

	v2_filter FilterV2 (
		.clk                                                  (clk),
		.reset                                                (reset),
		.input_data                                           (output_data_exp_sig_gen),
		.output_data                                          (output_data_v2));

	v3_filter FilterV3 (
		.clk                                                  (clk),
		.reset                                                (reset),
		.input_data                                           (output_data_exp_sig_gen),
		.output_data                                          (output_data_v3));

	v4_filter FilterV4 (
		.clk                                                  (clk),
		.reset                                                (reset),
		.input_data                                           (output_data_exp_sig_gen),
		.output_data                                          (output_data_v4));

	v5_filter FilterV5 (
		.clk                                                  (clk),
		.reset                                                (reset),
		.input_data                                           (output_data_exp_sig_gen),
		.output_data                                          (output_data_v5));

	v6_filter FilterV6 (
		.clk                                                  (clk),
		.reset                                                (reset),
		.input_data                                           (output_data_exp_sig_gen),
		.output_data                                          (output_data_v6));
//-----------------------------------------------------------------------------
endmodule
